The semiconductor integrated circuit that has mounted on the same substrate together a field-effect transistor provided in a gate insulating structure with a memory holding layer and a field-effect transistor not provided in a gate insulating structure with a memory holding layer is known in the following types.
As the first conventional example, a nonvolatile memory array circuit is proposed, which circuit uses as a control transistor a field-effect transistor not provided in a gate insulating structure with a memory holding layer and possessing no memory holding function, uses as a nonvolatile memory transistor a field-effect transistor provided in a gate insulating structure with a memory holding layer containing a ferroelectric layer and configures an array structure having a multiplicity of such memory transistors arranged regularly longitudinally and laterally (refer, for example, to Patent Document 1).
As the second conventional example, a programmable nonvolatile logic array circuit has been known, which circuit arranges in the form of an array field-effect transistors not provided in a gate insulating layer with a memory holding layer and possessing no memory holding function, possesses as a selection transistor a field-effect transistor provided in a gate insulating structure with a memory holding layer containing a ferroelectric layer, selects part of the field-effect transistors possessing no memory holding function with the field-effect transistor provided in a gate insulating structure with a memory holding layer and mutually connects the selected field-effect transistors to construct a logical circuit, and subjects the information of this connection to nonvolatile memory (refer, for example, to Patent Document 2).
As the third conventional example, a nonvolatile logic circuit has been proposed, which circuit constructs a latch circuit with field-effect transistors provided in a gate insulating structure with a memory holding layer and causes a result of operation taking place in a logical operation circuit constructed with field-effect transistors not provided in a gate insulating structure with a memory holding layer and possessing no memory holding function to be memorized in the latch circuit (refer, for example, to Patent Document 3).
Patent Document 1: JP-A 2001-229685
Patent Document 2: JP-A HEI 09-107041
Patent Document 3: JP-A 2000-077986